F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/01/2024
Document Table of Contents

3.3.6. Register Map IP-XACT Support

When you generate the F-Tile PMA/FEC Direct PHY Intel® FPGA IP using Quartus® Prime Pro Edition software version 22.2 or later, the IP-XACT information for the IP is included in the <ip_name>.ip file. The generated IP-XACT information includes the register map about your IP. If your design uses FGT PMA, then the FGT register map is included in the <ip_name>.ip file and similarly for FHT PMA and soft CSR registers.

Use the following steps to generate the register map information in IP-XACT format:

  1. In the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, enable the Enable datapath Avalon® interface, Enable Direct PHY soft CSR and Enable PMA Avalon® Interface in the Avalon® Memory-Mapped Interface tab.
  2. Click Generate and check your <ip_name>.ip file.