F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier 3.14.1.3. TX Equalizer Settings 3.14.1.4. TX Error Injection 3.14.1.5. RX Reconvergence 3.14.1.6. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts A. Modify the Script for Device Initialization and Toolkit Bring-Up B. Modifying the Script to Run BER and Eye Measurement Tests C. Modifying the Script to Run Autosweep Test 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. F-Tile Production Revision OPNs A.2. OSC_CLK_1 QSF Assignment Requirement
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

7.6.2. Modifying the Scripts

There are several variables inside the script, such as setting up the channel links, PRBS pattern, loopback mode, BER test duration, and the TX equalizer settings that you must modify based on your design configuration. You must set the values of these variables in the script before running the test. The following procedures describes the steps to modify the script for each test:

A. Modify the Script for Device Initialization and Toolkit Bring-Up

You must modify the device initialization script and update the device that are on the JTAG chain and point to the .sof that you have programmed.
  1. Open device_initialization.tcl script in any text editor.
  2. Make the following modifications to the device_initialization.tcl script:
    set path <sof-file-path>
set result_dir <my_diretory>
set device_die_name <device-name>
An example of the settings in the device_initialization.tcl script is shown in the following figure.
Figure 148. Device Initialization Settings
Note: If you are using the Windows platform, use the .sof file name instead of sof file path in step 2 above.

B. Modifying the Script to Run BER and Eye Measurement Tests

Refer to the Transceiver Toolkit Scripts table to select the Transceiver Toolkit script for your desired mode.
  1. Choose the script based on your design mode and open it in any text editor.
  2. Make the following modifications to the script:
    • Set 1 to enable the test you want to run as shown below:
      ############### Tests to run: 0 = bypass, 1 = run ############### 
set run_ber_test 1
set run_eye_test 0
    • Set up the test variables. There are six main variables that you need to modify in the link_test_parameters list in the script:
      • TX logical channel (index 0)
      • RX logical channel (index 1)
      • PRBS pattern (index 2 and 3)
      • Loopback mode (index 4)
      • TX and RX PMA settings (index 5 to 11)
      • Eye measurement settings (index 12 to 15)
      Note: Currently the Transceiver Toolkit only supports RX PMA auto-adaptation mode. You can leave the RX PMA settings to the default values.
      For example, if you want to run the BER test between TX channel 0 and RX channel 0, set both index 0 and index 1 to value 0. You can also link TX and RX channels in different physical channel locations. For example, to link TX channel 0 to RX channel 1, set index 0 to value 0 and index 1 to value 1. In order to link TX and RX channels with different physical locations, make sure you have an external loopback, either through a loopback cable or card on the board. An example of the link_test_parameters settings is shown below:
      ####################################################
###      Customize the test variable             ###
####################################################
# The list_test_parameters' indexing :
#   index 0 - TX Logical Channel
#   index 1 - RX Logical Channel
#   index 2 - TX PRBS Generator Pattern : 
#             PRBS7,PRBS9,PRBS10,PRBS13,PRBS15,PRBS23,PRBS28,
#              PRBS31,QPRBS13,PRBS13Q,PRBS31Q,SSPR,SSPR1,SSPRQ
#   index 3 - RX PRBS Checker Pattern : PRBS7,PRBS9,PRBS10,PRBS13,
#             PRBS15,PRBS23,PRBS28,PRBS31,QPRBS13,PRBS13Q,PRBS31Q,
#             SSPR,SSPR1,SSPRQ
#   index 4 - Loopback Mode : PMA TX to RX Buffer lbpk - "TX2RXBUF"
#                           ; PMA TX to RX parallel lpbk  - "TX2RXPAR" 
#                           ; PMA RX to TX parallel lpbk  - "RX2TXPAR"
#   index 5 - TX Pre-Tap 2  :  {0 to 7}  
#   index 6 - TX Pre-Tap 1  :  {0 to 15}  
#   index 7 - TX Main Tap   :  {0 to 46}    
#   index 8 - TX Post-Tap 1 :  {0 to 19}  
#   index 9 - RX High Freq VGA Gain  :  {0 to 127}  
#   index 10 - RX High Freq Boost  :  {0 to 63}  
#   index 11 - RX DFE Data Tap 1   :  {0 to 63}    
#   index 12 - Enabling the eye height test : Enable - "true"  ;
#                                             Disable - "false"
#   index 13 - Set the Bit Error Rate to measure Eye Height :
#              Min - 1.0E-1  Maximum - 1.0E-12 
#   index 14 - Enabling the eye width test :
#              Enable - "true"  ;  Disable - "false"
#   index 15 - Set the Bit Error Rate to measure Eye Width : 
#              Min - 1.0E-1 Maximum - 1.0E-12

set link_test_parameters {{0 0 "PRBS23" "PRBS23" "TX2RXBUF" "0" "0" "0" 
  "0" "0" "0" "0" "true"  "1.0E-4" "true" "1.0E-4"}
						  {1 1 "PRBS9"  "PRBS9"  "TX2RXBUF" "0" "0" "0"
  "0" "0" "0" "0" "true"  "1.0E-4" "true" "1.0E-4"}}
      Note: The example above depicts the settings for two links only. If you want to run the test for four links, you have to add two more rows in the link_test_parameters list accordingly.
    • You must set the criteria to stop the BER test for a channel, either based on maximum error bits or the BER test duration. The following code shows an example on how to have the BER test stop after 6 seconds and displays the status of the link every 2 seconds. The max_error_bits indicates the maximum number of error bits encountered by the link. The test stops after reaching the maximum number of error bits even if the maximum run time of 6 seconds has not elapsed.
      ############### Setup link run length ###########################
set max_error_bits 10 
set max_run_time_in_seconds 6
set checker_status_polling_interval_in_seconds 2

C. Modifying the Script to Run Autosweep Test

  1. Choose the script based on your design mode and open it in any text editor.
  2. Make the following modifications to the script:
    • Set up the test variables for TX and RX PMA sweep range. There are seven main variables you need to modify in the link_test_parameters list in this script:
      • TX logical channel (index 0)
      • RX logical channel (index 1)
      • PRBS pattern (index 2 and 3)
      • Loopback mode (index 4)
      • Input parameters (index 5 to 11)
      • Output metric (index 12 to 17)
      • BER test duration (index 18)
      For example, to add BER as the output metric, set index 12 to value 1 as shown below:
      ####################################################
###      Customize the test variable             ###
####################################################
# The list_test_parameters' indexing :
#   index 0 - TX Logical Channel
#   index 1 - RX Logical Channel
#   index 2 - TX PRBS Generator Pattern : PRBS7,PRBS9,PRBS10,PRBS13,
#             PRBS15,PRBS23,PRBS28,PRBS31,QPRBS13,PRBS13Q,PRBS31Q,
#             SSPR,SSPR1,SSPRQ
#   index 3 - RX PRBS Checker Pattern : PRBS7,PRBS9,PRBS10,PRBS13,
#             PRBS15,PRBS23,PRBS28,PRBS31,QPRBS13,PRBS13Q,PRBS31Q,
#             SSPR,SSPR1,SSPRQ
#   index 4 - Loopback Mode : PMA TX to RX Buffer lbpk - "TX2RXBUF"  
#                            ; PMA TX to RX parallel lpbk  - "TX2RXPAR" 
#                           ; PMA RX to TX parallel lpbk  - "RX2TXPAR"
#   index 5 - TX Pre-Tap 2  :  {0 to 7}  if you put like 0:5 it 
#             autosweeps the channel for each number start from 0 to 5
#   index 6 - TX Pre-Tap 1  :  {0 to 15}  
#   index 7 - TX Main Tap   :  {0 to 46}    0,1.5 0,5,6
#   index 8 - TX Post-Tap 1 :  {0 to 19}  
#   index 9 - RX High Freq VGA Gain  :  {0 to 127}  
#   index 10 - RX High Freq Boost  :  {0 to 63}  
#   index 11 - RX DFE Data Tap 1   :  {0 to 63}    
#   index 12 - Adding BER matric :  "1"  ;  Disable - "0"
#   index 13 - Adding total height measurement matric :
#              Enable - "1"  ;  Disable - "0"
#   index 14 - Adding eye width time matric :
#              Enable - "1"  ;  Disable - "0"
#   index 15 - Adding eye width UI matric : 
#              Enable - "1"  ;  Disable - "0"
#   index 16 - Extrapolarate Rate:
#              Min - 1E-1  ;  Max - 1E-12 
#   index 17 - Extrapolarate Width Rate: 
#              Min - 1E-1  ;  Max - 1E-12 
#   index 18 - BER test duration per case (seconds): Max 1E3

set link_test_parameters {{0 0 "PRBS23" "PRBS23" "TX2RXBUF" "0:0" 
"0:1" "0:1" "0:0" "0:0" "0:0" "0:0" "1" "0" "0" "0" "1e-4" "1e-4" "2" }
						  {1 1 "PRBS10" "PRBS10" "TX2RXBUF" "0:0" 
"0:1" "0:0" "0:0" "0:0" "0:0" "0:0" "1" "0" "0" "0" "1e-4" "1e-4" "2" }}
    • You can get the Autosweep test data in xml format. The command shown below is in the Autosweep script and you can change the file name and result directory to your own file name and directory.
      autosweep_get_data -outputfile <result-directory>/<file-name>.xml $autosweep_inst_id
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