F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/01/2024
Document Table of Contents

3.11.2. FHT PMA Register Map

The FHT PMA Register Map contains the PMA analog registers, user clock settings, debug and loopback registers, PRBS pattern generator and checker registers, error injection and BER measurement registers for the FHT lanes.

You must enable the Enable PMA Avalon® interface setting under the PMA Avalon® Memory-Mapped Interface section in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor to access the FHT PMA registers.