F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/01/2024
Document Table of Contents FHT Deserializer

The deserializer clocks in serial input data from the receiver buffer using the high-speed serial recovered clock, and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS or FPGA core. The deserializer supports the following deserialization factors: 32, 64, and 128.

Figure 42. Deserializer