F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/01/2024
Document Table of Contents

A.2. OSC_CLK_1 QSF Assignment Requirement

Starting with Quartus® Prime Pro Edition software version 23.4, the software enforces a check for the appropriate .qsf assignment required to constrain the device’s OSC_CLK_1 pin for projects which contain transceivers in the design. Failure to provide this .qsf assignment causes the compilation to fail with the following error:
Intel FPGA IP instantiated in the design require the DEVICE_INITIALIZATION_CLOCK 
option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file
In order to avoid this error, the following .qsf assignment must be present in your project’s *.qsf file:
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK <OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ>
The frequency selected for this assignment must match the frequency you have provided for your device’s OSC_CLK_1 pin. For example, if you have provided a 125 MHz clock on your device’s OSC_CLK_1 pin, the assignment must be as shown below:
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ

The assignment can either be made directly in your project’s .qsf file using a text editor or using the Quartus® Prime Pro Edition software GUI at the following path:

Assignments -> Device -> Device and Pin Options -> General -> Configuration clock source

The following figure shows the setting in the Quartus® Prime Pro Edition software GUI.
Figure 155.  OSC_CLK_1 Setting in Quartus® Prime Pro Edition Software GUI