Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.1.1.1. RTL Changes for Use Case 1

Apply the following RTL changes to implement M20K memory protection for the Partial Reconfiguration with the PR Region Controller IP use case 1.
  1. Instantiate a separate PR Region Controller IP for each PR partition in your design. Place these IP in the static region of your design.
  2. Connect the control side of the PR region controller IPs to the host controller, using either the CSR or direct signal interface. These connections include the new m20k_ce_ctl_req signal that you provide, or its equivalent control bit in the PR Region Controller IP CSR. Implement this connection once for each PR partition.
  3. Connect the PR partition side signal of the PR region controller IP to the respective PR partition and surrounding logic that must be frozen:
    1. This connection includes the new m20k_ce_ctl signal from the PR region controller, which you must connect to an input port on the PR partition module instance.
    2. The m20k_ce_ctl signal can remain unconnected inside the PR partition.
    3. The m20k_ce_ctl signal must not pass through any freeze bridge, it must be applied directly to the PR partition.
    4. There is no requirement for the name of the signal or the name of the port that you connect.
    5. Add the m20k_ce_ctl signal, regardless of whether M20Ks are present in the base persona, to support possible future personas that do contain M20Ks.
    Note: You must not allow promotion of the provided signal to the global signal (clock) network. If the Compiler automatically promotes the signal to the global signal (clock) network, use the following assignment to disable that the promotion:
    set_instance_assignment -name GLOBAL_SIGNAL OFF -to \
    <hierarchical path name of the driving node of the signal>
  4. You must apply the M20K_CE_CONTROL_FOR_PR assignment to the input port that you connect to the m20k_ce_ctl signal. This assignment serves as a landmark for the Intel Quartus Prime software to identify this signal during subsequent steps.
  5. Modify the host controller logic to correctly control the m20k_ce_ctl_req signal, relative to stopping and starting the PR partition logic, applying freeze to the adjacent interfaces, applying region_reset, and the PR operation.
    Figure 89. PR Region Controller IP Connections and Landmark Assignments (CSR Interface)
    Figure 90. PR Region Controller IP Connections and Landmark Assignments (Direct Interface)

Did you find the information on this page useful?

Characters remaining:

Feedback Message