Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/03/2023

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Document Table of Contents

A.1.1.2. Compilation for Use Case 1

The following steps occur during compilation to implement M20K memory protection for the Partial Reconfiguration with the PR Region Controller IP use case 1:
  1. During the base and implementation revision compiles, for each PR partition, the Compiler detects the input port that has the M20K_CE_CONTROL_FOR_PR assignment.
  2. The Compiler inserts the CE logic between the input port that has the M20K_CE_CONTROL_FOR_PR assignment, and all M20Ks in the PR partition.

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