2.7.5. Creating Wrapper Logic for PR Regions
During the PR compilation, the Compiler converts each of the non-global ports on interfaces of the PR region into boundary port wire LUTS. The naming convention for boundary port wire LUTs are <input_port>~IPORT for input ports, and <output_port>~OPORT for output ports. For example, the instance name of the wire LUT for an input port with the name my_input, on a PR region with the name my_region, is my_region|my_input~IPORT.
- Manually floorplan the boundary ports using Logic Lock region assignments, or place the boundary ports automatically using the Fitter. The Fitter places the boundary ports during the base revision compile. The boundary LUTs are invariant locations the Fitter derives from the persona you compile. These LUTs represent the boundaries between the static region and the PR routing and logic. The placement remains stationary regardless of the underlying persona, because the routing from the static logic does not vary with a different persona implementation.
- To constrain all boundary ports within a given region, use a wildcard assignment. For example:
set_instance_assignment -name PLACE_REGION "65 59 65 85" -to \ u_my_top|design_inst|pr_inst|pr_inputs.data_in*~IPORT
This assignment constrains all the wire LUTS corresponding to the IPORTS that you specify within the place region, between the coordinates (65 59) and (65 85).Figure 25. Wire-LUTs at the PR Region Boundary
Optionally, floorplan the boundary ports down to the LAB level, or individual LUT level. To floorplan to the LAB level, create a 1x1 Logic Lock PLACE_REGION constraint (single LAB tall and a single LAB wide). Optionally, specify a range constraint by creating a Logic Lock placement region that spans the range. For more information about floorplan assignments, refer to Floorplan the Partial Reconfiguration Design.
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