Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/03/2023

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Document Table of Contents

A.1.1.3. Operation in Hardware for Use Case 1

When the design is running in hardware, you initiate the following sequence of operations around the PR operation. You must modify the host controller to implement steps 4 and 6 below. The remaining steps are a typical of the PR operation sequence.

  1. Stop the PR region.
  2. Freeze any AXI or Avalon bridges and other logic on the boundary of the PR region.
  3. Assert reset to the PR region
  4. Assert the m20k_ce_ctl_req signal for the PR region.
  5. Initiate the PR operation in the PR controller and wait for PR to complete.
  6. De-assert the m20k_ce_ctl_req signal and wait 10ns plus five clock cycles of the slowest clock in the PR partition (must be the slowest clock used for M20Ks in the PR partition).
  7. De-assert reset to the PR region.
  8. Unfreeze the bridges and logic around the PR region.
  9. Start the PR region.