Intel® FPGA Programmable Acceleration Card D5005 Board Management Controller User Guide

ID 683811
Date 11/04/2019
Public

1.4. Power Sequence Management

The BMC Power sequencer state machine is used to manage programmable acceleration card power-on and power-off sequences, to handle different corner cases during power-on process or normal operation. Intel® MAX® 10 power-up flow covers the entire process including Intel® MAX® 10 boot-up, Nios® II boot-up, and power sequence management for FPGA configuration. The host needs to check the build versions of both Intel® MAX® 10 and FPGA, and the Nios® II status every time after a power-cycle, and then takes corresponding actions in case the Intel® FPGA PAC D5005 runs into corner cases such as a Intel® MAX® 10/FPGA factory build load failure or Nios® II boot up failure.

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