Intel® FPGA Programmable Acceleration Card D5005 Board Management Controller User Guide

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ID 683811
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction 2. PLDM over MCTP SMBus 3. EEPROM Data Format 4. Revision History
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction x
1.1. About this document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Power Sequence Management 1.5. Board Monitoring Through Sensors 1.6. Secure Remote System Update 1.7. FRUID EEPROM 1.8. MAC Address EEPROM
2. PLDM over MCTP SMBus x
2.1. SMBus Slave Address 2.2. SMBus Interface Speed 2.3. MCTP Packetization Support 2.4. Supported Command Sets 2.5. PLDM Topology and Hierarchy 2.6. Board Monitoring through I2C SMBus
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction
2. PLDM over MCTP SMBus
3. EEPROM Data Format
4. Revision History

2. PLDM over MCTP SMBus

The BMC on the Intel® FPGA PAC D5005 communicates with a server BMC over the PCIe* SMBus.

The supported protocol is the Platform Level Data Model (PLDM) over Management Component Transport Protocol (MCTP) stack.

The Intel® FPGA PAC D5005 BMC supports a subset of the PLDM and MCTP commands to enable a server (motherboard) BMC to obtain sensor data such as voltage, current and temperature.

The BMC supports version 1.3.0 of the MCTP Base Specification (DMTF specification DSP0236) and version 1.1.1 of the PLDM for Platform Monitoring and Control standard (DMTF specification DSP0248).


Section Content
SMBus Slave Address
SMBus Interface Speed
MCTP Packetization Support
Supported Command Sets
PLDM Topology and Hierarchy
Board Monitoring through I2C SMBus

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