Intel® FPGA Programmable Acceleration Card D5005 Board Management Controller User Guide

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ID 683811
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction 2. PLDM over MCTP SMBus 3. EEPROM Data Format 4. Revision History
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction
1.1. About this document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Power Sequence Management 1.5. Board Monitoring Through Sensors 1.6. Secure Remote System Update 1.7. FRUID EEPROM 1.8. MAC Address EEPROM
2. PLDM over MCTP SMBus
2.1. SMBus Slave Address 2.2. SMBus Interface Speed 2.3. MCTP Packetization Support 2.4. Supported Command Sets 2.5. PLDM Topology and Hierarchy 2.6. Board Monitoring through I2C SMBus
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction
2. PLDM over MCTP SMBus
3. EEPROM Data Format
4. Revision History

1.5. Board Monitoring Through Sensors

The Intel® MAX® 10 BMC monitors voltage, current and temperature of various components on the Intel® FPGA PAC D5005. Host BMC can access the telemetry data through PCIe SMBus. The PCIe SMBus between the host BMC and Intel® FPGA PAC D5005 Intel® MAX® 10 BMC is shared by both: PLDM over MCTP SMBus endpoint and standard I2C slave to Avalon-MM interface (read-only).

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