Intel® FPGA Programmable Acceleration Card D5005 Board Management Controller User Guide

ID 683811
Date 11/04/2019
Public

3. EEPROM Data Format

This section is used to define data format of both FRUID EEPROM and MAC Address EEPROM that can be accessed by host and FPGA respectively.

MAC EEPROM Access

MAC EEPROM can only be read by Intel® MAX® 10 BMC or Intel® Stratix® 10 FPGA (but not from the host).

The MAC Address EEPROM only contains the starting 6-byte MAC address at address 0x00h followed by the MAC address count of 08. The starting MAC address is also printed on the label sticker on the back side of the Printed Circuit Board (PCB). From the starting MAC address, the remaining seven MAC addresses are obtained by sequentially incrementing the Least Significant Byte (LSB) of the starting MAC Address by a count of one for each subsequent MAC address.

Example:

Starting MAC: 644C360F4430

Count: 08

Subsequent MAC:

644C360F4431

644C360F4432

644C360F4433

644C360F4434

644C360F4435

644C360F4436

644C360F4437

FRUID EEPROM

  • FRUID EEPROM (0xA0) can be read only from the host BMC via PCIe* SMBus.

The structure in the FRUID EEPROM is based on the IPMI specification, Platform Management FRU Information Storage Definition, v1.3, March 24, 2015, from which a board information structure is derived. The FRUID EEPROM follows the common header format with Board Area and Product Info Area.

The common header bytes are placed from the first address of the EEPROM. The layout will look like the figure below. In the case of FRUID EEPROM, after factory programming, write protect will be enabled; no updates are possible to any of the EEPROM contents.

Figure 3. FRUID EEPROM Memory Layout Block Diagram
Table 4.  Board Area of FRUID EEPROM
Field Length in Bytes Field Description Field Values Field Encoding
1

Board Area Format Version

7:4 - reserved, write as 0000b

3:0 - format version number

0x01 Set to 1h (0000 0001b)
1 Board Area Length (in multiples of 8 bytes) 0x0B 88 bytes (includes 2 pad 00 bytes)
1 Language Code 0x00

Set to 0 for English

Note: No other languages supported at this time
3

Mfg. Date / TimeNumber of minutes from 0:00 hrs 1/1/96.

Least Significant byte first (little endian)

00_00_00h = unspecified

0x10

0x65

0xB7

Time difference between 12:00 AM 1/1/96 to 12 PM 11/07/2018 is 12018960 minutes = b76510h – stored in little endian format
1 Board Manufacturer type/length byte 0xD2

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 010010b (18 bytes of data)

P Board Manufacturer bytes

0x49

0x6E

0x74

0x65

0x6C

0xAE

0x20

0x43

0x6F

0x72

0x70

0x6F

0x72

0x61

0x74

0x69

0x6F

0x6E

8-bit ASCII + LATIN1 coded

Intel Corporation

1 Board Product Name type/length byte 0xD5

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 010101b (21 bytes of data)

Q Board Product Name bytes

0x49

0x6E

0x74

0x65

0x6C

0xAE

0x20

0x46

0x50

0x47

0x41

0x20

0x50

0x41

0x43

0x20

0x44

0x35

0x30

0x30

0x35

8-bit ASCII + LATIN1 coded

Intel® FPGA PAC D5005

1 Board Serial Number type/length byte* 0xCC

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 001100b (12 bytes of data)

N Board Serial Number bytes*

0x46

0x38

0x42

0x43

0x31

0x32

0x30

0x30

0x41

0x42

0x32

0x45

8-bit ASCII + LATIN1 coded

1st 6 hex digits are OUI: F8BC12

2nd 6 hex digits are MAC address: 00AB2E

Note: This is coded as an example and will need to be modified in an actual device
1 Board Part Number type/length byte 0xCE

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 001110b (14 bytes of data)

M Board Part Number bytes

0x4B

0x31

0x39

0x30

0x36

0x32

0x2D

0x30

0x30

0x33

0x52

0x30

0x2E

0x33

8-bit ASCII + LATIN1 coded with BOM ID. Specific example in cell alongside

K19062-003R0.3

Note: this is coded as an example and will need to be modified in an actual device.
1 FRU File ID type/length byte 0x00

8-bit ASCII + LATIN1 coded

7:6 – 00b

5:0 – 000000b (0 bytes of data)

The FRU File ID bytes field that should follow this is not included as the field would be ‘null’.

Note: FRU File ID bytes. The FRU File version field is a pre-defined field provided as a manufacturing aid for verifying the file that was used during manufacture or field update to load the FRU information. The content is manufacturer-specific. This field is also provided in the Board Info area. Either or both fields may be ‘null’.
1 MMID type/length byte 0xC6

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 000110b (6 bytes of data)

Note: This is coded as an example and will need to be modified in an actual device
M MMID bytes

0x41

0x42

0x31

0x32

0x33

0x34

Formatted as 6 hex digits. Specific example in cell alongside

AB1234

1 C1h (type/length byte encoded to indicate no more info fields). 0xC1
Y 00h - any remaining unused space 0x00
1 Board Area Checksum (zero checksum) 0x9F
Note: The checksum in this table is a zero checksum computed for the values used in the table. It must be recomputed for the actual values of a Intel® FPGA PAC D5005
Table 5.  Product Info Area of FRUID EEPROM
Field Length in Bytes Field Description Field Values Field Encoding
1

Product Area Format Version

7:4 - reserved, write as 0000b

3:0 - format version number = 1h for this specification

0x01 Set to 1h (0000 0001b)
1 Product Area Length (in multiples of 8 bytes) 0x0A Total of 80 bytes
1 Language Code 0x00

Set to 0 for English

Note: No other languages supported at this time
1 Manufacturer Name type/length byte 0xD2

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 010010b (18 bytes of data)

N Manufacturer Name bytes

0x49

0x6E

0x74

0x65

0x6C

0xAE

0x20

0x43

0x6F

0x72

0x70

0x6F

0x72

0x61

0x74

0x69

0x6F

0x6E

8-bit ASCII + LATIN1 coded

Intel Corporation

1 Product Name type/length byte 0xD5

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 010101b (21 bytes of data)

M Product Name bytes

0x49

0x6E

0x74

0x65

0x6C

0xAE

0x20

0x46

0x50

0x47

0x41

0x20

0x50

0x41

0x43

0x20

0x44

0x35

0x30

0x30

0x35

8-bit ASCII + LATIN1 coded

Intel® FPGA PAC D5005

1 Product Part/Model Number type/length byte 0xCE

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 001110b (14 bytes of data)

O Product Part/Model Number bytes

0x42

0x44

0x2D

0x41

0x43

0x44

0x2D

0x44

0x35

0x30

0x30

0x35

0x2D

0x31

8-bit ASCII + LATIN1 coded

OPN for the board

BD-ACD-D5005-1

1 Product Version type/length byte 0x01

8-bit binary

7:6 – 00b

5:0 – 000001b (1 byte of data)

R Product Version bytes 0x00

This field is encoded as family member

1 Product Serial Number type/length byte* 0xCC

8-bit ASCII + LATIN1 coded

7:6 – 11b

5:0 – 001100b (12 bytes of data)

P Product Serial Number bytes*

0x46

0x38

0x42

0x43

0x31

0x32

0x30

0x30

0x41

0x42

0x32

0x45

8-bit ASCII + LATIN1 coded

1st 6 hex digits are OUI: F8BC12

2nd 6 hex digits are MAC address: 00AB2E

Note: This is coded as an example and will need to be modified for a specific Intel® FPGA PAC instance
1 Asset Tag type/length byte 0x01

8-bit binary

7:6 – 00b

5:0 – 000001b (1 byte of data)

Q Asset Tag 0x00 Not supported
1 FRU File ID type/length byte 0x00

8-bit ASCII + LATIN1 coded

7:6 – 00b

5:0 – 000000b (0 bytes of data)

The FRU File ID bytes field that should follow this is not included as the field would be ‘null’.

Note: FRU The FRU File version field is a pre-defined field provided as a manufacturing aid for verifying the file that was used during manufacture or field update to load the FRU information. The content is manufacturer-specific. This field is also provided in the Board Info area. Either or both fields may be ‘null’.
1 C1h (type/length byte encoded to indicate no more info fields). 0xC1
Y 00h - any remaining unused space 0x00
1 Product Info Area Checksum (zero checksum) 0xB9
Note: the checksum in this table is a zero checksum computed for the values used in the table. It must be recomputed for the actual values of a Intel® FPGA PAC

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