Intel® FPGA Programmable Acceleration Card D5005 Board Management Controller User Guide

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ID 683811
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction 2. PLDM over MCTP SMBus 3. EEPROM Data Format 4. Revision History
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction x
1.1. About this document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Power Sequence Management 1.5. Board Monitoring Through Sensors 1.6. Secure Remote System Update 1.7. FRUID EEPROM 1.8. MAC Address EEPROM
2. PLDM over MCTP SMBus x
2.1. SMBus Slave Address 2.2. SMBus Interface Speed 2.3. MCTP Packetization Support 2.4. Supported Command Sets 2.5. PLDM Topology and Hierarchy 2.6. Board Monitoring through I2C SMBus
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction
2. PLDM over MCTP SMBus
3. EEPROM Data Format
4. Revision History

2.3. MCTP Packetization Support

MCTP Definitions

  • The message body represents the payload of an MCTP message. The message body can span multiple MCTP packets.
  • MCTP packet payload refers to the portion of the message body of an MCTP message that is carried in a single MCTP packet.
  • Transmission Unit refers to the size of the portion of the MCTP packet payload.

Transmission Unit Size

  • The baseline transmission unit (minimum transmission unit) size for MCTP is 64 bytes.
  • All MCTP control messages are required to have a packet payload that is no larger than the baseline transmission unit without negotiation. (The negotiation mechanism for larger transmission units between endpoints is message type-specific and is not addressed in MCTP Base specification)
  • Any MCTP message whose message body size is bigger than 64 bytes shall be split into multiple packets for a single message transmission.

MCTP Packet Fields

Figure 2. Generic Packet/Message Fields
Level Two Title