AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
ID
683803
Date
7/31/2018
Public
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Bus LVDS (BLVDS) extends the capability of LVDS point-to-point communication to multipoint configuration. Multipoint BLVDS offers an efficient solution for multipoint backplane applications.
Series | Family | I/O Standard |
---|---|---|
Stratix® | Intel® Stratix® 10 |
|
Stratix® V |
|
|
Stratix® IV | ||
Stratix® III | ||
Arria® | Intel® Arria® 10 |
|
Arria® V |
|
|
Arria® II | ||
Cyclone® | Intel® Cyclone® 10 GX |
|
Intel® Cyclone® 10 LP | BLVDS | |
Cyclone® V |
|
|
Cyclone® IV | BLVDS | |
Cyclone® III LS | ||
Cyclone® III | ||
MAX® | Intel® MAX® 10 | BLVDS |
Note: The programmable drive strength and slew rate features in these devices allow you to customize your multipoint system for maximum performance. To determine the maximum data rate supported, perform a simulation or measurement based on your specific system setup and application.