Intel® FPGA Voltage Sensor IP Core User Guide

ID 683781
Date 2/09/2018
Public
Document Table of Contents

3.1. Voltage Sensor Controller Core

The voltage sensor controller core contains a command register and conversion sequence data. You can use the command register to configure your intended conversion mode. This core also contains control logic which communicates with the voltage sensor hard IP block. You can access the register through the Avalon Memory-Mapped (Avalon-MM) slave interface. This core uses the Avalon Streaming (Avalon-ST) interface to send responses.

Figure 1. Voltage Sensor Controller Block Diagram

This voltage sensor controller core receives commands through the Avalon-MM slave control and status register (CSR) interface. The command includes mode and sequences. This core decodes the command and drives the signals that are connected to the voltage sensor controller core accordingly.

The voltage sensor controller core supports the following sequences. You can select the channels by using the following mode (MD) bits setting.

Table 3.  Channels Selection
MD1 MD0 Channel Channel Mapping
0 0 Channel 2 VCC
Channel 3 VCCP
Channel 4 VCCPT
Channel 5 VCCERAM
Channel 6 VCCL_HPS
Channel 7 ADCGND
0 1 Channel 0 VSIG[P,N]_0
Channel 1 VSIG[P,N]_1
Channel 2 VCC
Channel 3 VCCP
Channel 4 VCCPT
Channel 5 VCCERAM
Channel 6 VCCL_HPS
Channel 7 ADCGND
1 0 Channel 0 VSIG[P,N]_0
Channel 1 VSIG[P,N]_1
1 1 User select mode Defined by user

This core allows you to monitor separate channels. You can configure the sequences during run time.

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