Intel® FPGA Voltage Sensor IP Core User Guide

ID 683781
Date 2/09/2018
Public
Document Table of Contents

4.2. Response Interface

The interface type is Avalon-ST.

Table 5.  Response Interface
Signal Width Description
response_valid 1 Indicates from the source port that current data is valid.
response_channel[2:0] 3

Indicates which channel the voltage sample data corresponds to.

  • Bits 16:8 — not used.
  • Bits 7:0 — Channel 7 to Channel 0.
response_data[5:0] 6 Voltage sample data.
response_startofpacket 1 When asserted, indicates the start of a packet.
response_endofpacket 1 When asserted, indicates the last cycle of a packet.

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