Intel® FPGA Voltage Sensor IP Core User Guide

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ID 683781
Date 2/09/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Voltage Sensor IP Core Overview 2. Intel® FPGA Voltage Sensor IP Core Getting Started 3. Intel® FPGA Voltage Sensor IP Core Functional Description 4. Intel® FPGA Voltage Sensor IP Core Interface Signals 5. Intel® FPGA Voltage Sensor IP Core Registers 6. Intel® FPGA Voltage Sensor IP Core Implementation Guide 7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide
2. Intel® FPGA Voltage Sensor IP Core Getting Started x
2.1. Specifying Parameters and Options 2.2. Intel® FPGA Voltage Sensor Parameters
3. Intel® FPGA Voltage Sensor IP Core Functional Description x
3.1. Voltage Sensor Controller Core 3.2. Sample Storage Core 3.3. Configuring the Voltage Sensor Controller
3.1. Voltage Sensor Controller Core x
3.1.1. Conversion Modes
3.1.1. Conversion Modes x
3.1.1.1. One Round Conversion 3.1.1.2. Continuous Conversion
3.3. Configuring the Voltage Sensor Controller x
3.3.1. Configuring the Voltage Sensor Controller with Avalon-MM Sample Storage 3.3.2. Configuring the Voltage Sensor Controller with External Sample Storage
4. Intel® FPGA Voltage Sensor IP Core Interface Signals x
4.1. CSR Interface 4.2. Response Interface 4.3. Interrupt Interface
5. Intel® FPGA Voltage Sensor IP Core Registers x
5.1. Voltage Controller Core Registers 5.2. Sample Store Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide x
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access 6.1.2. Voltage Sensor Transfer Function
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access x
6.1.1.1. Configuration Registers for the Core Access Mode
6.1.1.1. Configuration Registers for the Core Access Mode x
6.1.1.1.1. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11 6.1.1.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
1. Intel® FPGA Voltage Sensor IP Core Overview
2. Intel® FPGA Voltage Sensor IP Core Getting Started
3. Intel® FPGA Voltage Sensor IP Core Functional Description
4. Intel® FPGA Voltage Sensor IP Core Interface Signals
5. Intel® FPGA Voltage Sensor IP Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide
7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide

6.1.1.1.1. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11

The following timing diagram shows the IP core timing to access the voltage sensor when MD[1:0] is not equal to 2'b11.

Figure 8. Timing Diagram when MD[1:0] is not Equal to 2'b11


  1. A low-to-high transition on the corectl signal enables the core access mode.
    Wait for a minimum of two clock cycles before proceeding to step 2.
  2. De-asserting the reset signal releases the voltage sensor from the reset state.
    Wait for a minimum two clock cycles before proceeding to step 3.
  3. Configure the voltage sensor by writing the configuration registers and asserting the coreconfig signal for eight clock cycles. The configuration register access mode is 8 bits and configuration data is shifted in serially.
  4. The coreconfig signal going low indicates the start of the conversion based on the configuration defined in the configuration register.
  5. Poll the eoc and eos status signals to check if conversion for the first channel defined by MD[1:0] is complete. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
  6. Poll the eoc and eos status signals to check if conversion for the subsequent channels defined by MD[1:0] are complete. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
  7. Repeat step 6 until the eos signal is asserted, indicating the completion of the conversion of one cycle on the channels specified by MD[1:0].
    1. Both the eoc and eos signals are asserted on the same clock cycle when the voltage sensor completes the conversion for the last channel.
    2. You can only interrupt the operation of the voltage sensor by writing into the configuration register after one cycle of the eos signal completes.
  8. When the sequence completes, and if the corectl and reset signals remain unchanged, the conversion repeats the same sequence again until corectl is 0 and reset is 1. If you want to measure other sequences, repeat step 2 to step 7.
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