Intel® FPGA Voltage Sensor IP Core User Guide

ID 683781
Date 2/09/2018
Public
Document Table of Contents

5.1. Voltage Controller Core Registers

Table 7.  Controller Core Registers
Offset Register Name Bits Bit Name RO/RW Description Reset Value
0x0 Command 13..31 Reserved Reserved. 0x0
12 CAL RW

Determines whether the output data is using a calibrated or a non-calibrated value.

  • 0 specifies non-calibrated value
  • 1 specifies calibrated value

You must not use this bit to enable calibration.

0x0
11 BU1 RW

Unipolar selection for Channel 0 or 1.1

  • 0 specifies unipolar selection
0x0
10 BU0 RW 0x0
9 MD1 RW

Mode select for channel sequencer.

  • MD[1:0] = 2'b00 specifies channel sequencer cycles from Channel 2 to Channel 7
  • MD[1:0] = 2'b01 specifies channel sequencer cycles from Channel 0 to Channel 7
  • MD[1:0] = 2'b10 specifies channel sequencer cycles from Channel 0 to Channel 1
  • MD[1:0] = 2'b11 specifies channel in CHSEL to be converted
0x0
8 MD0 RW 0x0
7 Reserved Reserved. 0x0
4:6 CHSEL RW Specifies the channel to be converted and used when MD[1:0] = 2'b11. 0x0
3 Reserved Reserved. 0x0
1:2 MODE RW

Specifies the controller core's mode of operation.

  • MD[1:0] = 2'b11 to 2'b10 are reserved
  • MD[1:0] = 2'b01 specifies continuous voltage sensor conversion
  • MD[1:0] = 2'b00 specifies one round of voltage sensor conversion

Do not write to this address when the RUN bit is set. You must wait for the hardware to clear these bits before updating this address.

0x0
0 RUN RW

Control bit to trigger the sequencer core operation.

  • 1 specifies run
  • 0 specifies stop

When the Intel® Quartus® Prime software writes a 0 to this address, the controller core completes its current operation and clears this field.

0x0
1 Only Unipolar mode is supported.

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