Intel® FPGA Voltage Sensor IP Core User Guide

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ID 683781
Date 2/09/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Voltage Sensor IP Core Overview 2. Intel® FPGA Voltage Sensor IP Core Getting Started 3. Intel® FPGA Voltage Sensor IP Core Functional Description 4. Intel® FPGA Voltage Sensor IP Core Interface Signals 5. Intel® FPGA Voltage Sensor IP Core Registers 6. Intel® FPGA Voltage Sensor IP Core Implementation Guide 7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide
2. Intel® FPGA Voltage Sensor IP Core Getting Started x
2.1. Specifying Parameters and Options 2.2. Intel® FPGA Voltage Sensor Parameters
3. Intel® FPGA Voltage Sensor IP Core Functional Description x
3.1. Voltage Sensor Controller Core 3.2. Sample Storage Core 3.3. Configuring the Voltage Sensor Controller
3.1. Voltage Sensor Controller Core x
3.1.1. Conversion Modes
3.1.1. Conversion Modes x
3.1.1.1. One Round Conversion 3.1.1.2. Continuous Conversion
3.3. Configuring the Voltage Sensor Controller x
3.3.1. Configuring the Voltage Sensor Controller with Avalon-MM Sample Storage 3.3.2. Configuring the Voltage Sensor Controller with External Sample Storage
4. Intel® FPGA Voltage Sensor IP Core Interface Signals x
4.1. CSR Interface 4.2. Response Interface 4.3. Interrupt Interface
5. Intel® FPGA Voltage Sensor IP Core Registers x
5.1. Voltage Controller Core Registers 5.2. Sample Store Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide x
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access 6.1.2. Voltage Sensor Transfer Function
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access x
6.1.1.1. Configuration Registers for the Core Access Mode
6.1.1.1. Configuration Registers for the Core Access Mode x
6.1.1.1.1. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11 6.1.1.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
1. Intel® FPGA Voltage Sensor IP Core Overview
2. Intel® FPGA Voltage Sensor IP Core Getting Started
3. Intel® FPGA Voltage Sensor IP Core Functional Description
4. Intel® FPGA Voltage Sensor IP Core Interface Signals
5. Intel® FPGA Voltage Sensor IP Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide
7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide

5.2. Sample Store Core Registers

Table 8.  Sample Store Core Registers
Offset Register Name Bits RO/RW Description Reset Value
6:31 0:5
0x0 Voltage Sample Reserved SAMPLE RO Values correspond to Channel 0 for Offset 0x0 and Channel 7 for Offset 0x7 (based on the MD[0:1] setting). For more information, refer to the Controller Core Registers table. 0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Offset Register Name Bits Field RO/RW Description Reset Value
0x8 Interrupt Enable 1:31 Reserved RO Reserved 0x0
0 M_EOP RW

Enable bit for end-of-packet interrupt.

  • 1 specifies the corresponding interrupt is enabled
  • 0 specifies the corresponding interrupt is disabled
0x1
0x9 Interrupt Status 1:31 Reserved RO Reserved 0x0
0 EOP RW

End-of-packet interrupt.

  • 1 specifies a complete block of samples is received
  • Writing a 1 to this address clears this bit
0x1
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