Intel® FPGA Voltage Sensor IP Core User Guide

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ID 683781
Date 2/09/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Voltage Sensor IP Core Overview 2. Intel® FPGA Voltage Sensor IP Core Getting Started 3. Intel® FPGA Voltage Sensor IP Core Functional Description 4. Intel® FPGA Voltage Sensor IP Core Interface Signals 5. Intel® FPGA Voltage Sensor IP Core Registers 6. Intel® FPGA Voltage Sensor IP Core Implementation Guide 7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide
2. Intel® FPGA Voltage Sensor IP Core Getting Started x
2.1. Specifying Parameters and Options 2.2. Intel® FPGA Voltage Sensor Parameters
3. Intel® FPGA Voltage Sensor IP Core Functional Description x
3.1. Voltage Sensor Controller Core 3.2. Sample Storage Core 3.3. Configuring the Voltage Sensor Controller
3.1. Voltage Sensor Controller Core x
3.1.1. Conversion Modes
3.1.1. Conversion Modes x
3.1.1.1. One Round Conversion 3.1.1.2. Continuous Conversion
3.3. Configuring the Voltage Sensor Controller x
3.3.1. Configuring the Voltage Sensor Controller with Avalon-MM Sample Storage 3.3.2. Configuring the Voltage Sensor Controller with External Sample Storage
4. Intel® FPGA Voltage Sensor IP Core Interface Signals x
4.1. CSR Interface 4.2. Response Interface 4.3. Interrupt Interface
5. Intel® FPGA Voltage Sensor IP Core Registers x
5.1. Voltage Controller Core Registers 5.2. Sample Store Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide x
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access 6.1.2. Voltage Sensor Transfer Function
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access x
6.1.1.1. Configuration Registers for the Core Access Mode
6.1.1.1. Configuration Registers for the Core Access Mode x
6.1.1.1.1. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11 6.1.1.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
1. Intel® FPGA Voltage Sensor IP Core Overview
2. Intel® FPGA Voltage Sensor IP Core Getting Started
3. Intel® FPGA Voltage Sensor IP Core Functional Description
4. Intel® FPGA Voltage Sensor IP Core Interface Signals
5. Intel® FPGA Voltage Sensor IP Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide
7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide

6.1.1.1. Configuration Registers for the Core Access Mode

The core access configuration register is an 8-bit register.

Figure 7. Core Access Configuration Register


Table 10.  Description for the Core Access Configuration Register
Bit Number Bit Name Description
D0 MD0

Mode select for channel sequencer:

  • MD[1:0]=2'b00—channel sequencer cycles from channel 2 to channel 7
  • MD[1:0]=2'b01—channel sequencer cycles from channel 0 to channel 7
  • MD[1:0]=2'b10—channel sequencer cycles from channel 0 to channel 1
  • MD[1:0]=2'b11—controlled by IP core. Specify the channel to be converted on chsel[3:0].
D1 MD1
D2 BU0

Channel 0—Register bit that indicates channel 0. Set to "0".

D3 BU1

Channel 1—Register bit that indicates channel 1. Set to "0".

D4 NA

Reserved. Set to "0".

D5 NA

Reserved. Set to "0".

D6 CAL

Calibration enable bit. "0" indicates calibration is off. "1" indicates calibration is on. The calibration result does not include the final 12-bit converted data when calibration is off.

D7 NA

Reserved. Set to "0".

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