Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
ID
683763
Date
5/24/2022
Public
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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Intel® Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
6.1.5.2. Setting Up the Correct MSEL Switch State
Select Active Serial x4 (Fast mode) for CvP operation.
Configuration Scheme | MSEL[2:0] |
---|---|
AS (Fast mode - for CvP)4 | 001 |
Related Information
4 To support AS fast mode, the VCCIO_SDM of Intel® Agilex™ device must be fully ramped-up within 10ms to the recommended operating conditions. The delay between the device exiting POR and the SDM Boot-up is shorter for the fast mode compared to the normal mode. Therefore, AS fast mode is the recommended configuration scheme for CvP because the device can conform to the PCIe 100ms power-up-to-active time requirement.