Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 5/24/2022
Public

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Document Table of Contents

6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express

Follow these steps to generate the synthesis HDL files with CvP enabled:

  1. Open the Intel® Quartus® Prime Pro Edition software.
  2. On the Tools menu, click Platform Designer . The Open System window appears.
  3. For System, click + and specify a File Name to create a new platform designer system. Click Create.
  4. On the System Contents tab, delete the clock_in and reset_in components that appear by default.
  5. In the IP Catalog locate and double-click Intel P-tile Avalon-ST for PCI Express. The new window appears.
  6. On the IP Settings tab, specify the parameters and options for your design variation.
  7. On the Top-Level Settings tab, select the Enable CVP (Intel VSEC) option.
    Note: For R-Tile Avalon-ST for PCI Express, on the Top-Level Settings tab, select the Enable CVP (Intel VSEC) option.
    Note: For F-Tile Avalon-ST for PCI Express, on the PCIe0 Settings -> PCIe0 PCI Express/ PCI Capabilities -> PCIe0 VSEC tab, select the Enable CVP (Intel VSEC) option.
    Note: For devices that support two PCIe Hard IP block on the left, CvP application can use either one of the two PCIe Hard IP blocks on left side. This option is to enable the CvP application to either lower or upper PCIe Hard block. Subsequently, you must do the pin assignments properly to use either lower or upper PCIe Hard block for CvP application.
  8. On the Example Designs tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
  9. For Generated file format, only Verilog is available.
  10. Click the Generate Example Design button. The Select Example Design Directory dialog box appears. Click OK. The software generates Intel® Quartus® Prime project files for PCI Express reference design. Click Close when generation completes. An example design intel_pcie_ptile_ast_0_example_design is created in your project directory.
  11. Click Finish. Close your current project and open the generated PCI Express example design (pcie_ed.qpf).
  12. Complete your CvP design by adding any desired top-level design and any other required modules. You must ensure you do the pin assignments properly to use either lower or upper PCIe Hard block for CvP application.
    Note: Reference design for CvP initialization and update is not available in the current version of the Intel® Quartus® Prime software.

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