Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 5/24/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3.1. Vendor Specific Capability Header Register

Table 6.  Vendor Specific Capability Header Register (Byte Offset: 0xD00)
Bits Name Reset Value Access Description
[15:0] PCI Express* Extended Capability ID 0x000B RO PCIe* specification defined value for VSEC Capability ID.
[19:16] Version 0x1 RO PCIe* specification defined value for VSEC version.
[31:20] Next Capability Offset Variable RO Starting address of the next Capability Structure implemented, if any.

Did you find the information on this page useful?

Characters remaining:

Feedback Message