Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 5/24/2022
Public

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8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.05.24 21.4 Removed note about periphery image loading time and configuration from the Power-Up Sequence Timing in CvP Initialization Mode table.
2022.03.02 21.4
  • Updated the CvP System section. The option to enable either lower or upper PCIe Hard block CvP support is enabled in the PCIe Hard IP.
  • Added note for timing sequence i in the Power-Up Sequence Timing in CvP Initialization Mode table.
2021.12.13 21.4 Made the following change:
  • Added conditions used to validate the power-up sequence timing in PCIe* Wake-Up Time Requirement: For CvP Initialization Mode
2021.10.04 21.3 Made the following changes:
  • Revised CvP Support for Intel® Agilex™ Device Family table:
    • Added preliminary tag to the R-tile and F-tile content
    • Added note describing the REFCLK_GXP clock behavior in R-tile
  • Added 100ms PCIe* link up time requirement in CvP Initialization Mode.
  • Updated link for Download the OpenSource Linux CvP Downstream Driver in Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express.
  • Added Implementation of CvP Update Mode section and all related subsections.
2021.07.01 21.2
Sections Updated:
  • CvP Modes [CvP Support for Intel Agilex Device Family Table updated
  • Configuration Images [Periphery image and core image definitions updated]
  • CvP Driver Flow [CvP Driver Flow Flowchart updated]
  • Generating the Synthesis HDL files for FPGA P-Tile Avalon Streaming (Avalon-ST) for Express [Enable CVP information added in Step 7]
  • Setting up the CvP Parameters in Device and Pin Options [Step 2b updated]
  • Downstream open source CvP Driver [This is a new section]
  • Upstream open source CvP Driver [This is a new section]
  • Programming CvP Images [Step 7 and Step 8 updated]
2021.03.24 20.4
Sections Updated:
  • CvP Modes
  • CvP System
2020.12.14 20.4 Removed the SDM_IO15 pin documented in Table: CvP Pin Descriptions and Connection Guidelines.
2020.09.15 19.4
  • Added information about the supported tile in Table: CvP Support for Intel® Agilex™ Device Family.
  • Updated following figure and table in section For CvP Initialization Mode:
    • Figure: PCIe Timing Sequence in CvP Initialization Mode
    • Table: Power-Up Sequence Timing in CvP Initialization Mode
2020.01.07 19.4 Initial release.

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