Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 5/24/2022
Public

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6.1.5.3. Programming CvP Images

In Active Serial configuration mode, you must program the periphery image (.periph.jic) into your AS configuration device and then download the core image (.core.rbf) using the PCIe Link. You can use Active Serial x4 (Fast mode) to load .periph.jic into your selected CvP initialization enabled Intel® Agilex™ device.

After loading the periphery image, the Intel® Agilex™ device is triggered to reconfigure from AS to load it. The link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities. Follow these steps to program and test the CvP functionality:

  1. Plug the Intel® Agilex™ device PCIe* card into the PCI Express slot of the DUT PC and power it ON.
  2. Open the Intel® Quartus® Prime Tools menu and select Programmer.
  3. Click Auto Detect to verify that the Intel® FPGA Download Cable recognizes the Intel® Agilex™ device.
  4. Follow these steps to program the periphery image:
    1. Select Intel® Agilex™ device, and then right click None under File column and select Change File.
    2. Navigate to .periph.jic file and click Open.
    3. Under Program/Configure column, select the respective devices.
    4. Click Start to program the periphery image into flash.
  5. After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel® Agilex™ device PCIe* card.
  6. You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
  7. Follow these steps if you are using downstream driver::
    1. Copy the .core.rbf file to your working directory.
    2. Open a console in Linux. Change the directory to the same mentioned above where the file is copied.
    3. Program the core image by typing the following command:
      dd if=<filename>.core.rbf of=/dev/altera_cvp bs=4K
  8. Follow these steps if you are using upstream driver:
    1. Copy the .core.rbf file into /lib/firmware
    2. In the kernel source directory, running the following command to use the FPGA manager to configure the core image.
      • Run: su to get root access.
      • Run:
        echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name
        
  9. You can see your core image running on the Intel® Agilex™ device PCIe* card. Alternatively, print out the kernel message using the dmesg to ensure the CvP is completed successfully.

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