Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 5/24/2022
Public

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3.1. Single Endpoint

Use the single endpoint topology to configure a single FPGA. In this topology, the PCIe* link connects one PCIe* endpoint in the FPGA device to one PCIe* root port in the host.

Figure 3. Single Endpoint Topology

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