Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
ID
683763
Date
5/24/2022
Public
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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Intel® Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
3.2. Multiple Endpoints
Use the multiple endpoints topology to configure multiple FPGAs through a PCIe* switch. This topology provides you with the flexibility to select the device to be configured or update through the PCIe* link. You can connect any number of FPGAs to the host in this topology.
The PCIe* switch controls the core image configuration through the PCIe* link to the targeted PCIe* endpoint in the FPGA. You must ensure that the root port can respond to the PCIe* switch and direct the configuration transaction to the designated endpoint based on the bus/device/function address of the endpoint specified by the PCIe* switch.
Figure 4. Multiple Endpoints Topology