Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 5/24/2022
Public

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1.3. CvP Modes

The CvP configuration scheme supports the following modes:

  • CvP Initialization mode
  • CvP Update mode

CvP Initialization Mode

This mode configures the CvP PCIe* core using the peripheral image of the FPGA through the on-board configuration device. Subsequently, configures the core fabric and all GPIOs through PCIe* link.

Benefits of using CvP Initialization mode include:

  • Satisfying the PCIe* wake-up time requirement
  • Saving cost by storing the core image in the host memory

CvP Update Mode

In the CvP update mode, you reconfigure the entire device except the CvP PCIe* core after the device enters the user mode through full chip configuration or CvP initialization. The subsequent core image updates use the PCIe* link (the periphery must not change during CvP update).

The CvP update mode uses the same process as root partition reuse in block-based design, which allows you to reuse the device periphery.

Choose this mode if you want to update the core image for any of the following reasons:

  • To change core algorithms logic blocks
  • To perform standard updates as part of a release process
  • To customize core processing for different components that are part of a complex system
Note: The CvP update mode is available after the FPGA enters user mode. In user mode, the PCIe* link is available for normal PCIe* applications as well as to perform an FPGA core image update.
Table 1.  CvP Support for Intel® Agilex™ Device Family
Note: The R-Tile and F-Tile specifications are preliminary, pending the full silicon verification.
Supported Tile PCIe* Version Supported CvP Modes Recommended CvP Driver
P-Tile
Gen3 x16
Note: You can only select Gen 3 and above in PCIe* Hard IP, but the host can down-train the link to Gen 1 and Gen 2 if necessary.

Gen4 x16

CvP Initialization

CvP Update

Downstream
R-Tile
Gen3 1x16
Note: You can only select Gen 3 and above in PCIe* Hard IP, but the host can down-train the link to Gen 1 and Gen 2 if necessary.

Gen4 1x16

Gen5 1x16

CvP Initialization

CvP Update

Upstream
F-Tile
Gen3 1x16
Note: You can only select Gen 3 and above in PCIe* Hard IP, but the host can down-train the link to Gen 1 and Gen 2 if necessary.

Gen4 1x16

Gen3 1x8

Gen4 1x8

Gen3 1x4

Gen4 1x4

CvP Initialization

CvP Update

Upstream
Note: Upstream CvP driver is available from Kernel v4.14 onwards. Kernel v5.9 is tested on Ubuntu and Intel hardware pending full silicon characterization.
Note: Downstream CvP driver is tested on P-Tile with Kernel Version 4.16 on Ubuntu.
Note: P-Tile: CvP application supported from Intel® Quartus® Prime 20.4 onwards.
Note: When P-Tile PCI Express is used for CvP, it does not support bifurcation or multi-host feature.
Note: R-Tile & F-Tile: CvP application supported from Intel® Quartus® Prime 21.2 onwards.
Note: R-Tile: The REFCLK_GXR reference clock to the R-tile must be on when you want to reconfigure the device.

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