Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

ID 683747
Date 6/22/2020

2.5. Hardware Testing

In the hardware design example, you can program the IP core in internal serial loopback mode and generate traffic on the transmit side that loops back through the receive side.
Figure 7.  Low Latency E-Tile 40G Ethernet IP Hardware Design Example High Level Block Diagram

The Low Latency E-Tile 40G Ethernet hardware design example includes the following components:

  • Low Latency E-Tile 40G Ethernet Intel® FPGA IP core.
  • Client logic that coordinates the programming of the IP core, and packet generation and checking.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the Intel® System Console. You communicate with the client logic through the System Console.

Follow the procedure at the provided related information link to test the design example in the selected hardware.

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