1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
- Supports 40G Ethernet MAC/PCS IP core for E-tile transceiver using Intel® Stratix® 10 or Intel® Agilex™ device.
- Supports preamble pass-through and link training.
- Generates design example with MAC stats counters feature.
- Provides testbench and simulation script.
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