Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

ID 683747
Date 6/22/2020
Public
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2.1. Features

  • Supports 40G Ethernet MAC/PCS IP core for E-tile transceiver using Intel® Stratix® 10 or Intel® Agilex™ device.
  • Supports preamble pass-through and link training.
  • Generates design example with MAC stats counters feature.
  • Provides testbench and simulation script.