Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

ID 683747
Date 6/22/2020
Public
Give Feedback

2.4. Simulation

The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.
Figure 6.  Low Latency E-Tile 40G Ethernet Design Example Block Diagram

The simulation design example top-level test file is basic_avl_tb_top.sv. This file provides a clock reference clk_ref of 156.25 Mhz to the PHY. It includes a task to send and receive 10 packets.

Table 4.   Low Latency E-Tile 40G Ethernet Core Testbench File Descriptions

File Names

Description

Testbench and Simulation Files
basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
basic_avl_tb_top_nc.sv Top-level testbench file compatible with the NCSim simulator.
basic_avl_tb_top_msim.sv Top-level testbench file compatible with the ModelSim* simulator.
Testbench Scripts
run_vsim.do

The Mentor Graphics* ModelSim* script to run the testbench.

run_vcs.sh

The Synopsys* VCS* script to run the testbench.

run_vcsmx.sh

The Synopsys* VCS* MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench.

run_ncsim.sh

The Cadence NCSim script to run the testbench.

run_xcelium.sh The Cadence Xcelium* script to run the testbench.
The successful test run displays output confirming the following behavior:
  1. Waiting for RX clock to settle
  2. Printing PHY status
  3. Sending 10 packets
  4. Receiving 10 packets
  5. Displaying "Testbench complete."

The following sample output illustrates a successful simulation test run:


#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#TX enabled
#**Sending Packet    1...
#**Sending Packet    2...
#**Sending Packet    3...
#**Sending Packet    4...
#**Sending Packet    5...
#**Sending Packet    6...
#**Sending Packet    7...
#**Received Packet   1...
#**Sending Packet    8...
#**Received Packet   2...
#**Sending Packet    9...
#**Received Packet   3...
#**Sending Packet    10...
#**Received Packet   4...
#**Received Packet   5...
#**Received Packet   6...
#**Received Packet   7...
#**Received Packet   8...
#**Received Packet   9...
#**Received Packet   10... 
#**
#** Testbench complete.
#**
#*****************************************