Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide

2.6. Low Latency E-Tile 40G Ethernet Design Example Registers

Table 5.   Low Latency E-Tile 40G Ethernet Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console.
Word Offset Register Type
0x300-0x3FF PHY registers
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x800-0x8FF Statistics Counter registers - TX direction
0x900-0x9FF Statistics Counter registers - RX direction
0x1000-1016 Packet Client registers
Table 6.  Packet Client Registers You can customize the Low Latency E-Tile 40G Ethernet hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit [29:16]: Specify the upper limit of the packet size in bytes. This is only applicable to incremental mode.
  • Bit [13:0]:
    • For fixed mode, these bits specify the transmit packet size in bytes.
    • For incremental mode, these bits specify the incremental bytes for a packet.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. Set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Random mode
    • 01: Fixed mode
    • 10: Incremental mode
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, bit [1] of PKT_GEN_TX_CTRL register is used to turn off the packet generator.
  • Bit [7]:
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits) 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits) 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits) 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits) 0x8765 RW
0x1016 PKT_CL_LOOPBACK_RESET [0] MAC loopback reset. Set to the value of 1 to reset the design example MAC loopback. 1'b0 RW
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