Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

ID 683747
Date 6/22/2020

2.3. Functional Description

This section describes the 40G Ethernet MAC/PCS IP core using the Intel device in E-tile based transceiver.

In the transmit direction, the MAC accepts client frames and inserts inter-packet gap (IPG), preamble, the start of frame delimiter (SFD), padding, and CRC bits before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end.

In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY, performs checks, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.