2.7. Design Example Interface Signals
The Low Latency E-Tile 40G Ethernet testbench is self-contained and does not require you to drive any input signals.
This clock is driven by the board oscillator.
The hardware design example routes this clock to the input of an IOPLL on the device and configures the IOPLL to drive a 100 MHz clock internally.
|Drive at 156.25 MHz.
|Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
|Transceiver PHY output serial data.
|Transceiver PHY input serial data.
|Status signals. The hardware design example connects these bits to drive LEDs on the target board. Individual bits reflect the following signal values and clock behavior: