2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
4.1. Turbo Encoder
The 3GPP Turbo encoder uses a parallel concatenated convolutional code. A convolutional encoder encodes an information sequence and another convolutional encoder encodes an interleaved version of the information sequence. The Turbo encoder has two 8-state constituent encoders and one Turbo code internal interleaver. The Turbo encoder accepts K bits and outputs 3K+12 bits, having a natural code rate 1/3. The last 12 output bits of every packet are termination bits, which guarantee that the state of the encoder is back to state zero in the end of encoding process.
Figure 7. Turbo Encoder Block Diagram
The output from the turbo coder is:
X 0, Z 0, Z’ 0, X 1, Z 1, Z’ 1, ..., X K–1, Z K–1, Z’ K–1
- Bits X 0, X 1, ..., X K–1 are input to both the first 8-state constituent encoder and the internal interleaver (K is the number of bits).
- Bits Z 0, Z 1, ..., Z K–1 and Z’ 0, Z’ 1, ..., Z’ K–1 are output from the first and second 8-state constituent encoders.
- The bits output from the internal interleaver (and input to the second 8-state constituent encoder) are X’ 0, X’ 1, ..., X’ K–1.
- Additionally, encoder outputs 12 termination bits, X K , X K+1, X K+2, X’ K, X’ K+1, X’ K+2, Z K, Z K+1, Z K+2, Z’ K, Z’ K+1, Z’ K+2.
Turbo Encoder Data Format
Turbo Encoder Latency Calculation
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