Turbo Intel® FPGA IP User Guide

ID 683734
Date 9/30/2022
Public
Document Table of Contents
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1.1. Turbo Intel® FPGA IP Features

The Turbo Intel® FPGA IP offers the following features:
  • General features:
    • 3GPP LTE compliant with support for block sizes from 40 to 6,144.
    • 3GPP UMTS compliant with support for block sizes from 40 to 5,114.
    • C/MATLAB bit-accurate models for performance simulation or RTL test vector generation.
  • Decoder features:
    • Run time parameters for interleaver size and number of iterations.
    • Early termination with cyclical redundancy check (CRC).
    • Compile time parameters for the number of parallel engines, input precision.
    • Uses MaxLogMAP decoding algorithm.
    • Double-buffering for reduced latency real-time applications, which allows the decoder to receive data while processing the previous data block at compile time.
    • No external memory required.
  • Encoder features:
    • Run-time selectable interleaver block sizes.
    • Compile time parameters for standard (LTE or UMTS) and parallel encoding engines (1, 4 or 8) for high throughput and low latency.
    • Code rate 1/3 only. Use external rate matching for other code rates.
    • Double-buffering allows the encoder to receive data while processing the previous data block at compile time.