Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2022
Public

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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

2.5. Simulating the IP with the RTL Simulator

Before simulating, generate a design example from the IP parameter editor. No hardware example gets generated when you click Generate Example Design. If you upgrade the IP to a newer version, regenerate the example design.
  1. To run the simulation with Synopsys VCS® simulator, run vcsmx_setup.sh from <example_design_directory>\simulation_scripts\synopsys\vcsmx\ directory by typing the following commands: 
    >> source vcsmx_setup.sh
>> simv
  2. To run the simulation with Cadence NCSim® simulator, run ncsim_setup.sh from <example_design_directory>\simulation_scripts\cadence\ directory by typing the following command: 
    sh ./ncsim_setup.sh USER_DEFINED_ELAB_OPTIONS='"-timescale 1ps/1ps"' USER_DEFINED_SIM_OPTIONS='"-input \"@run; exit\""'
  3. To run the simulation with Xcelium® simulator, run xcelium_setup.sh from <example_design_directory>\simulation_scripts\xcelium\ directory by typing the following command: 
    sh ./xcelium_setup.sh USER_DEFINED_ELAB_OPTIONS='"-timescale 1ps/1ps"' USER_DEFINED_SIM_OPTIONS='"-input \"@run; exit\""'
  4. To run the simulation with the ModelSim or Questa® simulator, run msim_setup.tcl from <example_design_directory>\simulation_scripts\mentor\ directory by typing the following commands: 
    vsim -c do msim_setup.tcl
ld
run -all
  5. To run the simulation with Aldec® simulator. run rivierapro_setup.tcl from <example_design_directory>\simulation_scripts\aldec\ directory by typing the following commands: 
    vsim -c do rivierapro_setup.tcl
ld
run -all
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