Turbo Intel® FPGA IP User Guide

ID 683734
Date 9/30/2022
Document Table of Contents

3. Parameter Settings

You can customize the Turbo IP by specifying parameters in the IP parameter editor:
Table 7.  Parameters
Parameter Range Description
Turbo Specification
Standard LTE or UMTS Select LTE or UMTS.
Codec Type Encoder, Decoder Select an encoder or decoder.
Turbo Decoder Options
Number of Processors 2, 4, 8, 16, 32
Note: The UMTS supports only 2 and 4, and LTE supports 2, 4, 8, 16, 32.

Select the number of engines (N dec) that the decoder uses. The output width (W out) varies depending on the number of engines:

  • 8 bits for 8 engines or less,
  • 16 bits for 16 engines,
  • 32 bits for 32 engines
Note: For the UMTS the output width is always 1.
Number of LLRs per input 1 or 2 The number of data LLR per input symbol (N LLR). For two LLR the input symbols are Z’2 Z2 X2 Z’1 Z1 X1
Note: This parameter is not available if you select UMTS standard.
Width of the input LLRs 5, 6, 7, 8 The number of input bits (W LLR) to the decoder. Three of the bits are integer bits and the remaining bits are fractional bits:
  • 5-bit LLRs have two fractional bits.
  • 6-bit LLRs have three fractional bits.
  • 7-bit LLRs have four fractional bits.
  • 8-bit LLRs have five fractional bits.
Turbo Encoder Options
Parallelism of Encoder 1, 4, 8 Selects the number of parallel encoding engines (N enc) for LTE turbo encoder only.

For UMTS turbo encoder the value of this parameter (N enc) is 1.

This parameter is not available in the Intel® Quartus® Prime Standard Edition software IP variations.

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