2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
4.2.3. Decoder Latency Calculation
The decoding delay D is the number of clock cycles the IP core consumes to decode an entire block of data. D depends on the block size, the number of iterations to perform, and the number of engines available in the decoder.
The following calculations assume no early termination for the worst case latency.
You can calculate the decoding delay D using one of the following equations:
- D = 26 + (2 × f(K,N dec ) + 14) × 2 × I , if f(K, N dec ) <= 32
- D = 26 + (f(K,N dec ) + 46) × 2 × I , if f(K, N dec ) >= 32:
- K is the block size
- I is the number of decoding iterations
- N dec is the number of engines specified in the decoder
- f(K,N dec) = K/min(4, N dec), if K ≤ 128.
- f(K,N dec) = K/min(8, N dec), if 128 < K ≤ 512.
- f(K,N dec) = K/min(16, N dec), if 512 < K ≤ 1024.
- f(K,N dec) = K/N dec otherwise.
For UMTS, f(K,N dec) = ceil(K/N dec)
- D = 26 + (6144/8 + 46) × 2 × 8 = 13,050, if K = 6144, N dec = 8, I = 8.
- D = 26 + (2 × 40/4 + 14) × 2 × 8 = 544, if K = 40, N dec = 8, I = 8.
You can calculate the decoding latency (the time the decoder takes to decode an entire block to the decoded data is ready for output) using the following equation:
L = D/f s
Where f is the system clock speed.
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