Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.1.1. Turbo Encoder Data Format

The required input data ordering for a block of size K is: X 0, X 1, X 2, . . . . X K - 1. The output data is three bits wide.

Table 8.  Turbo Encoder Input Data Ordering for a Block of Size K
Output Data sink_data
Nenc = 8 Nenc = 4 Nenc = 1
0 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 3 X 2 X 1 X 0 X 0
1 X 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 1
... ... ... ..
K - 1 - - X K - 1
K/4-1 - X K-1 X K-2 X K-3 X K-4 -
K/8-1 X K-1 X K-2 X K-3 X K-4 X K-5 X K-6 X K-7 X K-8 - -
Table 9.  Turbo Encoder Output Data Ordering for a Block of Size K and Number of Parallel Encoder = 1
Output Data source_data
2 1 0
0 Z ’0 Z 0 X 0
1 Z ’1 Z 1 X 1
... ... ... ..
K - 1 Z ’ K - 1 Z K - 1 X K - 1
K X K + 1 Z K X K
K + 1 Z K + 2 X K + 2 Z K + 1
K + 2 X ’ K + 1 Z ’ K X ’ K
K + 3 Z ’ K + 2 X ’ K + 2 Z ’ K + 1
Note: The outputs of the last four clock cycles are corresponding to 12 termination bits.
Table 10.  Turbo Encoder Output Data Ordering for a Block of Size K and Nenc = 4Note: Parallelism of encoder is only supported in Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ device variations in Intel® Quartus® Prime Pro Edition software and not supported for Intel® Arria® 10 device variation in Intel® Quartus® Prime Standard Edition software.
Output Data source_data
11...8 7...4 3...0
0 Z ’3 Z ’2 Z ’1 Z’0 Z 3 Z 2 Z 1 Z 0 X 3 X 2 X 1 X 0
1 Z ’7 Z ’6 Z ’5 Z’4 Z 7 Z 6 Z 5 Z 4 X7X 6 X 5 X 4
... ... ... ..
K / 4 - 1 Z ’K-1 Z ’K-2 Z ’K-3 Z’K-4 Z K-1 Z K-2 Z K-3 Z K-4 X K-1 X K-2 X K-3 X K-4
K / 4 Z ’K+2 X ’K+1 Z K+2 X K+1 X ’K+2 Z ’K X K+2 Z K Z ’K+1 X ’K Z K+1 X K
Note: The outputs of the last four clock cycles are corresponding to 12 termination bits.
Table 11.  Turbo Encoder Output Data Ordering for a Block of Size K and Nenc = 8Note: The value of N enc can be 1, 4, or 8 in the Intel® Quartus® Prime Pro Edition software and the value is 1 in Intel® Quartus® Prime Standard Edition software . N enc is only supported in Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ device variations in Intel® Quartus® Prime Pro Edition software and not supported for Intel® Arria® 10 device variation in Intel® Quartus® Prime Standard Edition software.
Output Data source_data
23...16 15...8 7...0
0 Z ’7 Z ’6 Z ’5 Z’4 Z’3 Z’2 Z’1 Z’0 Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z 1 Z 0 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0
1 Z ’15 Z ’14 Z ’13 Z’12 Z’11 Z’10 Z’9 Z’8 Z 15 Z 14 Z 13 Z 12 Z 11 Z 10 Z 9 Z 8 X 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8
... ... ... ..
K / 8 - 1 Z ’K-1 Z ’K-2 Z ’K-3 Z’K-4 Z’K-5 Z’K-6 Z’K-7 Z’K-8 Z K-1 Z K-2 Z K-3 Z K-4 Z K-5 Z K-6 Z K-7 Z K-8 X K-1 X K-2 X K-3 X K-4 X K-5 X K-6 X K-7 X K-8
K / 8 4'bx Z ’K+2 X ’K+1 Z K+2 X K+1 4'bx X ’K+2 Z ’K X K+2 Z K 4'bx Z ’K+1 X ’K Z K+1 X K
Note: The outputs of the last clock cycles are corresponding to 12 termination bits. where output bits 23, 22, 21, 20, 15, 14, 13, 12, 7, 6, 5, 4 in the last clock cycle are unused bits.
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