2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
4.1.2. Turbo Encoder Latency Calculation
The encoding delay D is the number of clock cycles the IP core consumes to encode an entire block of data. If K is the block size, D = K/Nenc + 14, where Nenc is the number of parallel encoder. The encoding delay does not include the loading delay, which requires the same number of clock cycles as the block size K to load the input data to the input buffer.
- When K = 6144, and Nenc = 8, D = 6144/8 +14 = 782
- When K = 40, and Nenc = 1, D = 40 + 14 = 54
You can calculate the encoding latency (the time taken by the encoder to encode an entire block) using the following equation:
L= D/f s
Where f is the system clock speed.
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