Turbo Intel® FPGA IP User Guide

ID 683734
Date 9/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2. Turbo Encoder Latency Calculation

The encoding delay D is the number of clock cycles the IP core consumes to encode an entire block of data. If K is the block size, D = K/Nenc + 14, where Nenc is the number of parallel encoder. The encoding delay does not include the loading delay, which requires the same number of clock cycles as the block size K to load the input data to the input buffer.

For example:

  • When K = 6144, and Nenc = 8, D = 6144/8 +14 = 782
  • When K = 40, and Nenc = 1, D = 40 + 14 = 54

You can calculate the encoding latency (the time taken by the encoder to encode an entire block) using the following equation:

L= D/f s

Where f is the system clock speed.

The value of 4 or 8 is only available in Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ device variations in Intel® Quartus® Prime Pro Edition software.