1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
7.5.6.4.1. Timing Closure: Dynamic Reconfiguration
7.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
7.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
7.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
7.5.6.4.5. I/O Timing Violation
7.5.6.4.6. Internal FPGA Path Timing Violation
5.3.2.2. Output Path Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
group_oe_from_core | Input | Quarter-rate: 4 |
Output enable signal from FPGA core. Synchronous to the core_clk_out output from the IP. This signal is shared across all groups. |
group_<n>_data_from_core | Input | Quarter rate-DDR: 8 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH |
Data signal from FPGA core. Synchronous to the core_clk_out output from the IP. |
group_strobe_out_en | Input | Quarter-rate: 4 |
Strobe output enable from FPGA core. Synchronous to the core_clk_out output from the IP. This signal is shared across all groups. |
group_<n>_data_out /group_<n>_data_io | Output/Bidirectional | 1 to 34 | Data output from the IP. Synchronous to the group_<n>_strobe_out or group_<n>_strobe_io output from the IP. If the Pin Type parameter is set to Output, the group_<n>_data_out signals are used. If the Pin Type parameter is set to Bidirectional, the group_<n>_data_io signals are used. |
group_<n>_strobe_out/group_strobe_io/group_<n>_strobe_io | Output/Bidirectional | 1 | Positive output strobe from the IP. If the Pin Type is set to Output, the group_<n>_strobe_out signal is used. If the Pin Type is set to Bidirectional the group_<n>_strobe_io signal is used. |
group_<n>_strobe_out_n /group_<n>_strobe_io_n | Output/Bidirectional | 1 | Negative output strobe fro the IP. This is used if the Strobe Configuration is set to Differential. If the Pin Type is set to Output, the group_<n>_strobe_out_n signal is used. If the Pin Type is set to Bidirectional, the group_<n>_strobe_io_n signal is used. |