1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 3 C-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
7. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
8. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
9. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
7.5.6.4.1. Timing Closure: Dynamic Reconfiguration
7.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
7.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
7.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
7.5.6.4.5. I/O Timing Violation
7.5.6.4.6. Internal FPGA Path Timing Violation
1.2. Features
Features of the PHY Lite for Parallel Interfaces FPGA IPs:
- Support interface frequency range of 150 MHz to 1250 MHz (for Agilex™ 3, Agilex™ 5 and Agilex™ 7 M-Series devices) or 100 MHz to 1200 MHz (for Agilex™ 7 F-Series, Agilex™ 7 I-Series, and older devices).
- Support input, output, and bidirectional data channels.
- Support the DQS gating and ungating circuitry for strobe-based interfaces.
- Support output delays through interpolator.
- Support dynamic on-chip termination (OCT) control.
- Support quarter-rate, half-rate, and full-rate mode of the interface clock conversions.
- Support input, output, and read enable, strobe enable, and OCT enable paths.
- Support single and double data rates (SDR and DDR) at the I/Os.
- Support the PHY clock tree.
- Support dynamically reconfigurable delay chains using the Avalon® memory-mapped interface.
- Support process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
Note: For Stratix® 10, Arria® 10, and Cyclone® 10 GX devices, you can set the non-PVT compensated component of the input delay through Quartus Settings File (.qsf) assignment in the Quartus® Prime software.
Family | Cyclone® 10 GX, Arria® 10, Stratix® 10 | Agilex™ 7 F/I-Series | Agilex™ 7 M-Series, Agilex™ 5 D/E-Series, Agilex™ 3 C-Series |
---|---|---|---|
I/O Count | 48 per bank | 48 per sub-bank | 96 per bank |
Max # of groups | 18 | 4 | 8 |
Structure | Each Group must fit within 1 IO48 bank | IP must fit within 1 IO48 sub-bank | IP must fit within 1 IO96 bank |
Interface frequency range | 100 – 1200 MHz | 150 – 1250 MHz | |
Core clock rate | Selectable. The parameter clock rate of user logic allows you to choose (quarter, half, or full rate). | Not Selectable. Clock rate is auto-calculated. |
|
Data configuration | Single-ended/ Differential | Single-ended only | Single-ended/ Differential |
Reserved pins | No | Strobe only | Strobe and RZQ |
Auto pin assignment | No | Yes (data, strobe, and reference clock) | Yes (data, strobe, and RZQ) |
I/O Standard | SSTL-12 SSTL-125 SSTL-135 SSTL-15 SSTL-15 Class I SSTL-15 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V-HSTL Class I 1.2-V-HSTL Class II 1.5-V-HSTL Class I 1.5-V-HSTL Class II 1.8-V-HSTL Class I 1.8-V-HSTL Class II 1.2-V POD 1.2-V 1.5-V 1.8-V |
SSTL-12 1.2-V POD |
SSTL-12 1.2-V POD 1.1-V POD 1.2-V HSTL 1.2-V HSUL 1.1-V LVSTL 1.05-V LVSTL |
Ability to mix bidirectional and unidirectional group types in same IP instance | Yes | No | Yes |
Auto generate address register map | No | Yes | |
Resolution (based on VCO freq.) | 6.5104 - 13.0208 ps (output) 3.2522 - 6.5104 ps (input) |
6.25 - 13.0208 ps (output) 6.25 - 13.0208 ps (input) |
|
Delay range (based on VCO clock) |
6.5104 - 130.208 ps @1200 MHz (output) 0 - 1663.4 ps @1200 MHz (input)
9.7656 - 625 ps @100 MHz (output) 0 - 2495.1 ps @100 MHz (input) |
0 - 12.8 ns @1250 MHz (output) 0 - 12.8/24.0 ns @1250 MHz (input * )
0 - 26.67 ns @150 MHz (output) 0 - 26.67/50.00 ns @150 MHz (input * ) |
|
* Agilex™ 7 M-Series, Agilex™ 5 D/E-Series, and Agilex™ 3 C-Series input RcvEn/read_enable_offset. |