Key Advantages of MAX® 10 Devices
Summary of MAX® 10 Device Features
MAX® 10 Device Ordering Information
MAX® 10 Device Maximum Resources
MAX® 10 Devices I/O Resources Per Package
MAX® 10 Vertical Migration Support
Logic Elements and Logic Array Blocks
Analog-to-Digital Converter
User Flash Memory
Embedded Multipliers and Digital Signal Processing Support
Embedded Memory Blocks
Clocking and PLL
FPGA General Purpose I/O
External Memory Interface
Configuration
Power Management
Revision History for the MAX® 10 FPGA Device Overview
Hitless Update
The hitless update feature avoids glitches on the I/Os during reconfiguration to keep the operation of downstream devices unaffected.
The MAX® 10 devices support the following hitless update modes:
- JTAG mode—requires access to external JTAG pins
- Non-JTAG mode—does not require access to external JTAG pins and accessible through the internal JTAG interface and FPGA fabric (e.g., I2C soft IP)
The hitless update feature freezes the I/Os during reconfiguration and reconfigures the new image with the pre-defined I/O states. You can perform the hitless update through a series of instructions using JTAG (internal or external) and the Dual Configuration Intel® FPGA IP for non-JTAG mode respectively. For more information refer to AN 904: MAX® 10 Hitless Update Implementation Guidelines and AN 963: MAX® 10 Hitless Update Implementation Guidelines Using Internal JTAG Interface.