AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
ID
683380
Date
5/26/2023
Public
1.1. Introduction
1.2. Types of Intel® MAX® 10 Design Update Flow
1.3. Stages of Intel® MAX® 10 Hitless Update Flow
1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation
1.5. Hitless Update using Intel® Quartus® Prime Programmer
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player
1.7. Hitless Update Using Self-Developed Algorithm
1.8. Boundary-Scan Pattern Configuration Bit Location
1.9. JTAG Instructions
1.10. Sample of Hitless Update Algorithm in Jam Format
1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
Section Content
Introduction
Types of Intel MAX 10 Design Update Flow
Stages of Intel MAX 10 Hitless Update Flow
Intel MAX 10 Hitless Update Requirement and Limitation
Hitless Update using Intel Quartus Prime Programmer
Hitless Update using Intel Jam STAPL Byte-Code Player
Hitless Update Using Self-Developed Algorithm
Boundary-Scan Pattern Configuration Bit Location
JTAG Instructions
Sample of Hitless Update Algorithm in Jam Format
Document Revision History for AN 904: Intel MAX 10 Hitless Update Implementation Guidelines