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1.1. Introduction
1.2. Types of Intel® MAX® 10 Design Update Flow
1.3. Stages of Intel® MAX® 10 Hitless Update Flow
1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation
1.5. Hitless Update using Intel® Quartus® Prime Programmer
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player
1.7. Hitless Update Using Self-Developed Algorithm
1.8. Boundary-Scan Pattern Configuration Bit Location
1.9. JTAG Instructions
1.10. Sample of Hitless Update Algorithm in Jam Format
1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
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1.5. Hitless Update using Intel® Quartus® Prime Programmer
The Intel® Quartus® Prime Programmer does the following functions:
- Reads a user-specified input .ips file to hold each I/O to the desired state
- Performs real-time programming operation to write the configuration bitstream into the internal flash of the Intel® MAX® 10 FPGA
- Performs I/O state clamping control and initiates the configuration process.
Figure 2. Implementing Hitless Update using Intel® Quartus® Prime Programmer
To implement the hitless update through the Intel® Quartus® Prime programmer, you must create and execute a pin state information (.ips) file.
Note: You can use the created .ips file to program the device with any design, provided that it targets the same device and package. You must use the .ips file together with a POF file.