AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.9. JTAG Instructions

Table 2.  JTAG Instructions
Instruction Name Instruction Binary Description
SAMPLE/ PRELOAD 00 0000 0101
  • Permits an initial data pattern to be an output at the device pins.
  • Allows you to capture and examine a snapshot of signals at the device pins if the device is operating in normal mode.
EXTEST 00 0000 1111
  • Forces test pattern at the output pins and capture the test results at the input pins.
  • Allows you to test the external circuitry and board-level interconnects.
BYPASS 11 1111 1111
  • Places the 1-bit bypass register between the TDI and TDO pins.
  • Allows the BST data to pass synchronously through target devices to adjacent devices during normal device operation.
ISP_ENABLE_CLAMP 10 0011 0011 Enables ISP mode and forces all I/Os to follow the content of the JTAG boundary-scan register.
ISP_DISABLE 10 0000 0001 Disables ISP mode.
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