AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.2. Types of Intel® MAX® 10 Design Update Flow

The Intel® MAX® 10 FPGA provides various flexibility to perform updates on the Intel® MAX® 10 design. It enables you to select the correct configuration method that suits the needs of your system.
The following are the available configuration or programming methods:
  • In-system programming: You can program the internal flash including the configuration flash memory (CFM) and user flash memory (UFM) of the Intel® MAX® 10 devices with In-System Programming (ISP) through industry standard IEEE 1149.1 JTAG interface. ISP offers the capability to program, erase, and verify the CFM and UFM. The JTAG circuitry and ISP instructions for Intel® MAX® 10 devices comply to the IEEE-1532-2002 programming specification. The device can be reconfigured to the new image from the updated internal flash through power cycle or pulse nCONFIG signal. The device is out of user mode during the entire ISP process and all I/O pins remain tri-stated.
  • Real-time programming: The real-time ISP feature updates the internal flash with a new design image while the device is still operating in user mode. During the internal flash programming, the device continues to operate using the existing design. After the new design image programming process completes, the device does not reset. The new design image update takes effect in the next reconfiguration cycle.
  • Remote system updates: With the remote system upgrade feature, enhancements and bug fixes for FPGA devices can be done remotely by updating the internal flash through the On-Chip Flash Intel® FPGA IP core and perform reconfiguration from remote site through the Dual Configuration Intel® FPGA IP core.

However, all the internal flash programming methods require you to perform reconfiguration to get the new design running on the device. During the reconfiguration process, all the I/O pins can be either tri-stated or weak pull-up, depending on Intel® Quartus® Prime settings. Consequently, your system may be impacted if the downstream device relies on the status of the I/O pins of the Intel® MAX® 10 devices.

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