AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.3. Stages of Intel® MAX® 10 Hitless Update Flow

Intel® MAX® 10 device must enter user mode and drives the I/O pins to the desired state before performing hitless update.

At a high level, the Intel® MAX® 10 hitless update flow may be categorized into five stages:

  • Stage 1: I/O clamp through boundary-scan. The I/O state is setup based on real-time I/O state sampling or by shifting in predefined boundary-scan data to perform I/O clamp at desired state.
  • Stage 2: Internal flash programming. The Intel® MAX® 10 internal flash (CFM and UFM) is programmed and updated while the design is still running with the I/O pins clamped at a user-defined state. You can store critical design registers or finite state machine (FSM) values and desired I/O states values into the UFM before performing Stage 2.
  • Stage 3: Internal configuration. The I/Os remain in the desired state while the configuration takes place from the internal flash into CRAM.
  • Stage 4: Device initialization. After entering user mode, you have control on the period of time to release the I/Os clamp. During the defined period, you can unload the I/O state value, register or FSM value that previously stored in the User Flash Memory, force the user design logic into a correct state to output the same desired I/O value as the clamping state, to ensure no disruption to the system.
  • Stage 5: Normal user operation.
Figure 1. Stages of Intel® MAX® 10 Hitless Update
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